How to make code run differently depending on the platform it is running on?
xarzu - Apr 05 2019 09:17 AM
How do I set a breakpoint in an attached process in visual studio
xarzu - Apr 04 2019 11:47 AM
Recent Blog Entries
Recent Status Updates
- Managed C++
- Visual Basic 4 / 5 / 6
- linked list
- hello world
Posted 18 January 2013 - 07:50 AM
1. Smaller Instruction size
2. Smaller cpu cycles
3. Smaller memory cycles
4. Increase in multiprogramming
5. None of the above.
Can someone please give the answer with an explaination?
Posted 18 January 2013 - 08:47 AM
1. Smaller instruction size: For a particular CPU, you need an op code (machine instruction) for every operation the device is capable of. This might include a separate operation for each function in the ALU, a separate operation for fetching data from an I/O port, a separate operation for putting data onto an I/O port, a separate operation for moving data around to each available storage area, etc. With more capabilities built into the CPU, the size of the instruction set likely gets bigger.
2. "Smaller" CPU cycles doesn't really make sense. "Faster" CPU cycles, maybe? Or perhaps "smaller" is referring to the number of steps in the CPU cycle: Fetch op code, decode op code, evaluate address, memory read, execute, memory write. If you're trying to make the CPU cycles "smaller", I suppose you'd have to eliminate some unnecessary steps in that sequence. Which steps could be removed in the context of the question?
3. Smaller memory cycles: Again, I'm pretty sure this is supposed to read "Faster" memory cycles, because there's not much to be done to make a memory cycle "smaller". You must specify an address, wait for the data lines to stabilize, then transfer that data along the bus to another register. Writing is similar. Specify an address and provide the data, wait for the lines to stabilize, then active the "write" operation in the memory controller. That's already as small as it's going to get. Speeding this up can only effectively be done by either increasing the memory controller's clock rate, or by "pipelining" sequential reads or writes.
4. Increase in multiprogramming: Is this referring to Multi-core CPU's? Multi-core processors usually have a duplicate set of registers and ALU's alongside the first, and sometimes more than that (3 core, 4 core, 6 core, 8 core, etc.) A duplicate set allows one set of registers and ALU to work on one instruction while another simultaneously works on another.
So, in light of the above explanations, what do you think the answer is?
Edited by gregwarner, 18 January 2013 - 08:49 AM.
Posted 18 January 2013 - 09:36 PM
Posted 20 January 2013 - 09:18 AM