Can someoen help me find out whats wrong with my VHDL code please?

Okay, so I'm trying to write code for a 4-bit up then down counter. I want it to have four inputs (clk, rst, enable and short) and four outputs (cnt0,cnt1,cnt2 and cnt3). My out puts will feed into my seven-segment led decoder program that I have already designed and tested.
Desired operation of the counter
When (Enable = 1) I want the counter to count from 1 to 10 then back down to 1 on a continous cycle, but when (short = 1) I want it to count from 1 to 5 then back down to 1 on a continous cycle. When (Enable = 0) I want the counter to stay at it's current state. When (rst = 1) I want the counter to go back to state 1.

State diagram

Untitled-1.jpg 525.92K 146 downloads

After a writing my code I checked the the syntax and the following error messaged appeared...
ERROR:HDLParsers:823 - "C:/Users/Jimbob/Documents/Lab3/counter.vhd" Line 178. Choices have non compatible types.
ERROR:HDLParsers:811 - "C:/Users/Jimbob/Documents/Lab3/counter.vhd" Line 176. Choice s1 duplicated in case.

I'm finding it very difficult to work out what is wrong with my code, if any one can point out whats causing these errors I would be extremely gratefull.

code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity counter is
Port (
Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Enable : in STD_LOGIC;
Short : in STD_LOGIC;
Cnt3 : out STD_LOGIC;
Cnt2 : out STD_LOGIC;
Cnt1 : out STD_LOGIC;
Cnt0 : out STD_LOGIC
);
end counter;

architecture Behavioral of counter is
type eg_state_type is (s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18);
signal state_reg, state_next: eg_state_type;

begin

-- State register
process (Clk, Rst)
begin

if (Rst = '1') then state_reg <= s1;
elsif (clk' event and Clk = '1') then state_reg <= state_next;
end if;

case state_reg is
when s1 =>
if Enable= '1' then
State_next <= s2;
else state_next <= S1;
end if;

when s2 =>
if Enable= '1' then
State_next <= s3;
else state_next <= S2;
end if;

when s3 =>
if Enable= '1' then
State_next <= s4;
else state_next <= S3;
end if;

when s4 =>
if Enable= '1' then
State_next <= s5;
else state_next <= S4;
end if;

when s5 =>
if short= '1' then
state_next <= s15;
end if;
if Enable= '1' then
state_next <= s6;
else state_next <= s5;
end if;

when s6 =>
if Enable= '1' then
state_next <= s7;
else state_next <= s6;
end if;

when s7 =>
if Enable= '1' then
state_next <= s8;
else state_next <= s7;
end if;

when s8 =>
if Enable= '1' then
state_next <= s9;
else state_next <= s8;
end if;

when s9 =>
if Enable= '1' then
state_next <= s10;
else state_next <= s9;
end if;

when s10 =>
if Enable= '1' then
state_next <= s11;
else state_next <= s10;
end if;

when s11 =>
if Enable= '1' then
state_next <= s12;
else state_next <= s11;
end if;

when s12 =>
if Enable= '1' then
state_next <= s13;
else state_next <= s12;
end if;

when s13 =>
if Enable= '1' then
state_next <= s14;
else state_next <= s13;
end if;

when s14 =>
if Enable= '1' then
state_next <= s15;
else state_next <= s14;
end if;

when s15 =>
if Enable= '1' then
state_next <= s16;
else state_next <= s15;
end if;

when s16 =>
if Enable= '1' then
state_next <= s17;
else state_next <= s16;
end if;

when s17 =>
if Enable= '1' then
state_next <= s18;
else state_next <= s7;
end if;

when s18 =>
if Enable= '1' then
state_next <= s1;
else state_next <= s8;
end if;

end case;
end process;

-- Moore output logic
process (state_reg)
begin
case state_reg is

when s1|s2|s3|s4|s5|s6|s7|s11|s12|s13|s14|s15|s16|s17|s18 =>
cnt0 <= '0';
when s8|s9|s10 =>
cnt0 <= '1';

when s1|s2|s3|s8|s9|s10|s11|s12|s17|s18 =>
cnt1 <= '0';
when s4|s5|s6|s7|s13|s14|15|s16 =>
cnt1 <= '1';

when s1|s4|s5|s8|s9|s11|s12|s15|s16 =>
cnt2 <= '0';
when s2|s3|s6|s7|s10|s13|s14|s17|s18 =>
cnt2 <= '1';

when s2|s4|s6|s8|s10|s12|s14|s16|s18 =>
cnt3 <= '0';
when s1|s3|s5|s7|s9|s11|s13|s15|s17 =>
cnt3 <= '1';

end case;
end process;

end Behavioral;