8 replies to this topic

[Apprentice123]

What the result of this "if"?

[/COLOR][/SIZE][/FONT]variable a : std_logic_vector(4 downto 0) := (others => '0');
variable b : std_logic_vector(31 downto 0
[FONT=arial, sans-serif][SIZE=5][COLOR=#333333]
[/COLOR][/SIZE][/FONT]if b /= a then[FONT=arial, sans-serif][SIZE=5][COLOR=#333333]

[dargueta]

This looks like homework. We'll help with homework, but we won't do it for you. Do you know what /= does?

[Apprentice123]

dargueta said:

This looks like homework. We'll help with homework, but we won't do it for you. Do you know what /= does?

This is exactly what I'm asking. I know in C:
a /=b ==> a = a / b

But I do not know what is checked in the "if"

[dargueta]

Google is your friend. :)

VHDL Operators

[Apprentice123]

Thanks

dargueta said:

Google is your friend. :)

VHDL Operators

[RhetoricalRuvim]

Generally, in C, the following code would output 'abcd' :

int a; 

if (a= 0) printf ("dcba"); 

else printf ("abcd"); 

Whatever's inside the parentheses would get executed, and then the result gets compared to anything that can be defined as 'nothing' .

[dargueta]

/= is equivalent to != in C.

[RhetoricalRuvim]

dargueta said:

/= is equivalent to != in C.

Are you sure it's C?

[Alexander]

RhetoricalRuvim said:

Are you sure it's C?

/= in VHDL, not /= in C.

If I were to guess, I believe they try to describe the symbol ≠ (not equal) with slash-equal.