[VHDL] Troubles programming VDHL file for a chronometer

Dear Reader,

First of all my apologies for my English, but I’m doing my best.
For a school project I have to make an chronometer on an ALTERA UP2 Education Board.
All my counters (hundreds of seconds, seconds, minutes, hours) work fine on the board.
The problem is that I have only two 7 digit displays.
So I can only display hundreds of seconds or seconds, or minutes or hours.
I made all my counters with flipflops and logic gates since this was asked by my professor.
Now it is necessary that I make a control block that sends out the hundreds of seconds until this counter recycles (at 100).
Then I have to display the seconds until the seconds recycles (at 60). Then I have to display the minutes, and so on…. .
The problem in that since it’s kind of crazy work to make this with logic gates, we have to make this control block in VHDL.
Implementing the VHDL-block in my scheme with logic gates and flipflops is not a problem.
I already implemented a frequency divider to divide the frequency of my oscillator.
The problem is that I have to write this control block, and I’m not familiar with VHDL.
I already wrote down some code and compiled, recompiled, search for my faults, recompiled, … .
When I solved a problem there always was a new one.
I have spent many hours searching and debugging but, now I stuck.
So I was wondering if a nice person could help me find my faults.
I’m familiar with c# programming (advanced), c++ (basic), JavaScript(basic), actionscript(basic) and XML(basic) if that helps.

Please note that the inputs are all separate bits and not bit-vectors.
“HSecDoorlopen” is a boolean which says that the hundreds of seconds are passed and “Uur” is Dutch for Hours.
Also the hour-counter recycles at 23. (0-23 displayed).
Normally all inputs and outputs are active low, but for simplicity I putted them active high.
Also I have to implement 4 master signals by DIP-switches.
If the counter is for example displaying minutes, but I want to show to seconds by making the DIP-switch high (1), the seconds have to display and the counters needs to count further.
When no DIP-switch is selected (all 4 = 0), just display the standard mode where the highest counter that is counting will display (in this example back to minutes).
But I will be glad if I can display the standard mode, and I think I will find how to implement the DIP-switches myself, but all help is welcome.

Thanks in advance,
Warch

P.S. In attachment my VHDL-file and an image to visualize my education board.

entity Control is

port(I_Uur0, I_Uur1, I_Uur2, I_Uur3, I_Uur4, I_Uur5, I_Uur6, I_Uur7, I_Min0, I_Min1, I_Min2, I_Min3,  I_Min4,  I_Min5, I_Min6,  I_Min7, I_Sec0, I_Sec1, I_Sec2, I_Sec3, I_Sec4, I_Sec5, I_Sec6, I_Sec7, I_HSec0, I_HSec1, I_HSec2, I_HSec3, I_HSec4, I_HSec5, I_HSec6, I_HSec7:in bit; Q_0, Q_1, Q_2, Q_3, Q_4, Q_5, Q_6, Q_7: out bit);

end Control;


architecture behavior of Control is


begin

process(I_Uur0, I_Uur1, I_Uur2, I_Uur3, I_Uur4, I_Uur5, I_Uur6, I_Uur7, I_Min0, I_Min1, I_Min2, I_Min3,  I_Min4,  I_Min5, I_Min6,  I_Min7, I_Sec0, I_Sec1, I_Sec2, I_Sec3, I_Sec4, I_Sec5, I_Sec6, I_Sec7, I_HSec0,I_HSec1, I_HSec2, I_HSec3, I_HSec4, I_HSec5, I_HSec6, I_HSec7)


type HSecDoorlopen is (false);

type SecDoorlopen is (false);

type MinDoorlopen is (false);

type UurDoorlopen is (false);


begin


if(HSecDoorlopen = false)then

	Q_0 <= I_HSec0;

	Q_1 <= I_HSec1;

	Q_2 <= I_HSec2;

	Q_3 <= I_HSec3;

	Q_4 <= I_HSec4;

	Q_5 <= I_HSec5;

	Q_6 <= I_HSec6;

	Q_7 <= I_HSec7;

end if;


if((SecDoorlopen = false) and (HSecDoorlopen = true)) then

	Q_0 <= I_Sec0;

	Q_1 <= I_Sec1;

	Q_2 <= I_Sec2;

	Q_3 <= I_Sec3;

	Q_4 <= I_Sec4;

	Q_5 <= I_Sec5;

	Q_6 <= I_Sec6;

	Q_7 <= I_Sec7;

end if;


if(MinDoorlopen = false and SecDoorlopen = true)then

	Q_0 <= I_Min0;

	Q_1 <= I_Min1;

	Q_2 <= I_Min2;

	Q_3 <= I_Min3;

	Q_4 <= I_Min4;

	Q_5 <= I_Min5;

	Q_6 <= I_Min6;

	Q_7 <= I_Min7;

end if;


if(MinDoorlopen = true)then

	Q_0 <= I_Uur0;

	Q_1 <= I_Uur1;

	Q_2 <= I_Uur2;

	Q_3 <= I_Uur3;

	Q_4 <= I_Uur4;

	Q_5 <= I_Uur5;

	Q_6 <= I_Uur6;

	Q_7 <= I_Uur7;

end if;


if(I_HSec0 and (not I_HSec1) and (not I_HSec2) and I_HSec3 and I_HSec4 and (not I_HSec5) and (not I_HSec6) and I_HSec7)then

	HSecDoorlopen := true;

end if;


if(I_Sec0 and (not I_Sec1) and (not I_Sec2) and I_Sec3 and I_Sec4 and (not I_Sec5) and I_Sec6 and (not I_Sec7))then

	SecDoorlopen := true;

end if;


if(I_Min0 and (not I_Min1) and (not I_Min2) and I_Min3 and I_Min4 and (not I_Min5) and I_Min6 and (not I_Min7))then

	MinDoorlopen := true;

end if;


end process;

end behavior;