The make program essentially is used to update targets (exe or object files) according to the dependency instructions, typically present in a file called makefile. The program automatically can link dependent modules and also decide which files are to be (re)compiled by looking at the object code timestamps. Essentially make allows the compilation process to be a breeze.
The makefile contains all the dependency information required for compiling. The file is typically denoted as makefile or Makefile. This however can be overridden by specifying the file name with the -f switch. The instructions are written in single lines and interpreted accordingly. A backslash (\) can be used to signify continuation of the line.
The target is the final output that is required at the end of the make process. It typically is reliant on many other files to have compiled successfully. Target compilation are carried out by a series of actions called as command. Rule can be composed of multiple commands but each starting with a tab character.
Makefile has the feature of using variables, like in other programming languages. A variable is defined as:
variable_name = variable_definition
$(variable_name) is used to use its value.
Also like C/C++ make has the capability of including files by:
Make software also has set of internal macros:
List of all the defined dependencies, space separated, with duplicates
List of all the defined dependencies, space separated, without duplicates
Contains the name of the current target
Current prerequisite modified later than the current target
The makefile typically has the contents are specified below:
Lines with no text are ignored
Pound acts as a start of comments (single-line) indicator
targets: dependency; commands
Here the targets and their dependencies are specified. If the dependent files have not been created or a newer version of their source code exists, then the files are regenerated. These can be followed by one or more commands. If there are no dependencies then the commands are executed always.
The specified makefile is used as the description file
Print the help information
Ignore any errors
Prints the command that will be executed. For testing the flow of the compilation process.
Returns 0 if the target file is up to date; non-zero if otherwise
Prints out the variables and settings existing by default
Now to put all the above options to use. We will build a descriptor file to build an exe called sampleexec. Also assume that it needs two source files src1.c and src2.c. To build a descriptor for this and save it in a file called makefile.
The makefile will look like this
sampleexec : src1.o src2.o gcc -o sampleexec src1.o src2.o src1.o : src1.c gcc -c src1.c src2.o : src2.c gcc -c src2.cTo compile just run:
Steps make takes to compile sampleexec:
- sees that sampleexec depends on the object files src1.o src2.o
- looks for the target definition of the two object files.
- sees that src1.o depends on the file src1.c
- executes the commands given in src1.o's rule and compiles src1.c to get the object file.
- similarly looks at the target src2.o and compiles the object files
- prepares sampleexc by combining the two object files
This way any changes to the project can be done just to one file. This way errors and rework is reduced by a lot.
If you have any questions, please feel free to post them here!