Verilog? Any suggestions is greatly appreciated.

I'm building an ALU in verilog. The original given code was this: `
`define AND 4'b0000
`define OR 4'b0001
`define ADD 4'b0010
`define SLL 4'b0011
`define SRL 4'b0100
`define SUB 4'b0110
`define SLT 4'b0111
`define NOR 4'b1100

module ALU(BusW, BusA, BusB, ALUCtrl, Zero);

parameter n = 32;

output [n-1:0] BusW;
input [n-1:0] BusA, BusB;
input [3:0] ALUCtrl;
output Zero;

reg [n-1:0] BusW;

always @(ALUCtrl or BusA or BusB) begin
case(ALUCtrl)
`AND: begin
BusW <= #20 ...;
end
...
endcase
end
assign #1 Zero =
endmodule

it can be done in behavioral so i got up to this much and then i got confused with the rest of the xor, addi, ori, sll, slt (ignoring the over flow):

`define AND 4'b0000
`define OR 4'b0001
`define ADD 4'b0010
`define SLL 4'b0011
`define SRL 4'b0100
`define SUB 4'b0110
`define SLT 4'b0111
`define NOR 4'b1100

module ALU(busW, busA, busB, ALUCtrl, Zero);
output[31:0] busW;
input[31:0] busA, busB;
input[3:0] ALUCtrl;
output Zero;
reg[31:0] busW;
reg Zero;
always @(ALUCtrl or busA or busB) begin
case(ALUCtrl)
`AND: busW <= busA & busB;
`OR: busW <= busA | busB;
`ADD: busW <= busA + busB;
`SLL: busW <= busA << busB;
`SRL: busW <= busA >> busB;
`SUB: busW <= busA - busB;
`SLT: if (busA < busB) busW <= 1; else busW <= 0;
`NOR: busW <= ~(busA | busB);
endcase
end
//it was necessary to have this outside the previous always block
//otherwise it would not have been a combinational block just like we thought.
always @(busW) if (busW == 0) Zero <= 1; else Zero <= 0;
endmodule

module testbench;
reg[31:0] busA, busB;
reg[3:0] ALUCtrl;
wire[31:0] busW;
wire Zero;
ALU ALU1(busW, busA, busB, ALUCtrl, Zero); //instantiate ALU
initial begin
#1 ALUCtrl = 2; busA = 'h00000000; busB = 'h00000000;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 2; busA = 'h00000000; busB = 'hFFFFFFFF;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 2; busA = 'hFFFFFFFF; busB = 'h00000001;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 2; busA = 'h000000FF; busB = 'h00000001;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 6; busA = 0; busB = 0;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 6; busA = 1; busB = -1;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 6; busA = 1; busB = 1;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 7; busA = 0; busB = 0;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 7; busA = 0; busB = 1;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 7; busA = 0; busB = -1;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 7; busA = 1; busB = 0;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 7; busA = -1; busB = 0;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 0; busA = 'hFFFFFFFF; busB = 'hFFFFFFFF;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 0; busA = 'hFFFFFFFF; busB = 'hFFFFFFFF;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 0; busA = 'h00000000; busB = 'hFFFFFFFF;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 0; busA = 'h12345678; busB = 'h87654321;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 1; busA = 'hF0F0F0F0; busB = 'h0000FFFF;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 1; busA = 'h12345678; busB = 'h87654321;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 4; busA = 'h12345678; busB = 'h00000002;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 4; busA = 'h80000000; busB = 'h00000003;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 3; busA = 'h00000001; busB = 'h00000003;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
#1 ALUCtrl = 3; busA = 'h00001234; busB = 'h00000006;
#1 $display("ALUCtrl = 0x%x, busA = 0x%x, busB = 0x%x, busW = 0x%x, Zero = 0x%x", ALUCtrl, busA, busB, busW, Zero);
end
endmodule
Any help is greatly appreciated! thanks!