4 replies to this topic

[gammaman]

Did I code this full adder correctly given the following

Create a VHDL truth table program for a Full Adder. The adder has two inputs (A and B) and two outputs (Carry_Out and Sum).

Note: Carry out is not needed because I only have one Full Adder.

Library ieee;

use ieee.std_logic_1164.all;


Entity Truth_Table is

Port(

  A : in std_logic_vector (2 downto 0);

		S: out std_logic_vector (1 downto 0));

End Truth_Table;


Architecture Joe_Structure of Truth_Table is

Begin

with A select

    S<= "00" when "000",

             "01" when "001",

             "01" when "010",

             "10" when "011",

             "01" when "100",

             "10" when "101",

             "10" when "110",

             "11" when "111";

End Joe_Structure;

[WingedPanther]

Out of curiosity, what language is this in?

[John]

WingedPanther said:

Out of curiosity, what language is this in?

I believe it is in the name of the thread - VHDL. :P (something hardware description language)

[gammaman]

Yes the language is VHDL and it is used for hardware like adders, mux's, etc.

[John]

I had to design a very simple ALU using gates. Attached is my 4-Bit adder.

Attached Files

•  4-Bit-Adder.jpg   63.29K   4483 downloads